MOSFETs (metal-oxide-semiconductor field-effect transistors) are commonly used in electronic circuits, such as communication systems and power supplies. Power MOSFETs are particularly useful when used as electric switches to enable and disable the conduction of relatively large currents. The current flow for MOSFETs goes between conduction contacts, e.g., from the source to the drain. The RDSON (static drain-source on-resistance) should be minimized for power loss and heat dissipation. The power MOSFET switch is typically contained within a monolithic device for ease of integration and system design.
In one application, power MOSFETs are used in military and space electronic systems. These systems may be exposed to various forms of radiation including heavy ions, electrons, and high-energy protons. Conventional power MOSFETs could be irreparably damaged by radiation exposure. Radiation hardened semiconductor devices are typically used to protect against radiation exposure.
Radiation hardness is characterized by the application of various test conditions. A single event failure mode measures the MOSFET's ability to survive a single high energy heavy ion strike. The failure modes include single event burnout (SEB) and single event gate rupture (SEGR). The total dose of ionizing radiation measures the sensitivity of the MOSFET's device parameters to the total ionizing dose (TID).
FIG. 1 illustrates a conventional vertical power MOSFET semiconductor die 10. Gate structure 12 is coupled by bond wire 14 to a first pin of leadframe 16. Source regions 20 are formed in the surface of the die. Source contact pads 21 are formed over source regions 20. P-base regions 22 are electrically connected or shorted through P+ regions 23 to source contact pads 21. Source contact pads 21 are coupled by bond wire 24 to a second pin of leadframe 16. N-epitaxial region 26 and N+ substrate 27 operate as the drain region of the MOSFET. Semiconductor die 10 is mounted to a die flag of leadframe 16.
FIG. 2 illustrates a conventional lateral power MOSFET 30. Gate structure 32 is coupled by bond wire 34 to a first pin of leadframe 36. Source region 40 is formed in the surface of the die. Source contact pad 41 is formed over source region 40. P-base region 42 is electrically connected or shorted through P+ regions 43 to source contact pad 41. Source contact pad 41 is coupled by bond wire 44 to a second pin of leadframe 36. Drain region 46 is coupled through N+ region 47 and bond wire 48 to a third pin of leadframe 36. P-epitaxial region 50 is formed over P+ substrate 52.
An equivalent circuit is shown in FIG. 3. MOSFET 60 includes drain 62, source 64, and gate 66. A parasitic bipolar junction transistor 68 is formed by N+ region 20, P-base 22, P-epitaxial 26, and N+ region 27 in FIG. 1. In FIG. 2, the parasitic bipolar junction transistor 68 is formed by N+ region 40, P-base 42, P-epitaxial 50, and N+ region 47. Accordingly, transistor 68 has a collector coupled to drain 62 and an emitter coupled to source 64. Current source 70 represents the high current pulse from ionizing radiation. Resistor 72 is the resistance of P-epitaxial region 50.
In the SEB failure mode, exposure to ionizing radiation creates hole current flow through P-base 22 of MOSFET 10. The hole current flow from the ion strike effectively creates a current pulse through the resistance of P-base 22 which triggers the parasitic transistor. The localized high current density can thermally damage the MOSFET causing device failure. The same situation applies for the lateral MOSFET.
IN SEGR failure mode, exposure to ionizing radiation creates hole current flow through P-base 22 of MOSFET 10. Positive charge accumulates on the surface under gate structure 12. A high electric field is formed across the gate dielectric causing the film to rupture and the device to fail. Again, the same situation applies for the lateral MOSFET.